Time domain analysis for nonlinear-CMOS-gate-driven distributed RLC trees

This paper introduces a numerical method for time domain analysis of nonlinear-CMOS-gate-driven distributed RLC trees. During transition time, CMOS gates operate in seven regions according to the values of the input and output signal of gates. To include the carriers´ velocity saturation effect of short-channel devices, the alpha-power law model is used for MOS transistor modeling. Distributed RLC trees are used for modeling of tree-structured interconnects with transmission line effect into account. Based on the property of tree topology, an iterative method is proposed to simulate the system, in which each transmission line is simulated with FDTD method and the signals of CMOS gates are also discretized in time. Numerical results show that the proposed method is accurate and efficient, with the error less than 5% and the runtime much faster than SPICE.