• DocumentCode
    3164359
  • Title

    Performance driven placement with global routing for macro cells

  • Author

    Lim, Andrew ; Chee, Yeow Meng ; Wu, Ching-Ting

  • Author_Institution
    Inf. Technol. Inst., Singapore, Singapore
  • fYear
    1992
  • fDate
    28-29 Feb 1992
  • Firstpage
    35
  • Lastpage
    41
  • Abstract
    The authors present an effective performance driven placement with global routing algorithm for macro cells. Their algorithm is a hierarchical, divide and conquer, quad-partitioning approach. The quad-partitioning routine uses the Tabu search technique. Their algorithm uses the concept of proximity of regions to approximate the interconnection delays during the placement process. In addition, their algorithm can handle modules whose positions are fixed or are restricted to a particular subregion on the layout frame. The experimental results indicate the superiority of their placement in terms of quality of solutions and run times when compared to those by I. Lin and D. Du (1990)
  • Keywords
    VLSI; circuit layout CAD; search problems; Tabu search technique; VLSI technology; divide and conquer; global routing; hierarchical; interconnection delays; macro cells; performance driven placement; quad-partitioning approach; Circuit optimization; Compaction; Information technology; Integrated circuit interconnections; Partitioning algorithms; Propagation delay; Routing; Simulated annealing; Very large scale integration; Wires;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI, 1992., Proceedings of the Second Great Lakes Symposium on
  • Conference_Location
    Kalamazoo, MI
  • Print_ISBN
    0-8186-2610-0
  • Type

    conf

  • DOI
    10.1109/GLSV.1992.218367
  • Filename
    218367