Title :
CMOS implementation of a 32 b computer
Author :
Allmon, R.L. ; Bowhill, W.J. ; Benschneider, B.J. ; Brown, J.F. ; Cooper, E.M. ; Durdan, W.H. ; Fisher, A. ; Gavrielov, M.N. ; Gronowski, P.E. ; Grundmann, W.J. ; Herrick, W.V. ; Kravitz, D. ; Madden, L.C. ; Maheshwari, V.K. ; Marcello, R.C. ; Mills, G.G.
Author_Institution :
Digital Equipment Corp., Hudson, MA, USA
Abstract :
A four-chip custom VLSI implementation of a 32-b computer comprised of a CPU, a secondary cache controller, a floating-point accelerator, and a clock generator is described. It operates at a cycle time of 28 ns and is compatible with an existing computer architecture. The chip set is fabricated in a 1.5- mu m n-well, double-layer-metal CMOS process and includes over 650000 transistors. The CPU is a six-level pipeline engine built around three semiautonomous pipes. These provide simultaneous instruction prefetch and decode, specifier decode and execution, memory management, and I/O access. The CPU averages nine cycles/instruction on typical benchmarks. Chip functionality is verified through test vectors at the pins, with stuck-at fault coverage greater than 95%, and complete control store and cache tests. Summaries of process characteristics and physical specifications are presented.<>
Keywords :
CMOS integrated circuits; VLSI; application specific integrated circuits; microcomputers; microprocessor chips; pipeline processing; 1.5 micron; 28 ns; 32 bit; CPU; chip set; clock generator; double-layer-metal CMOS process; floating-point accelerator; four-chip custom VLSI implementation; microcomputer; n-well; secondary cache controller; six-level pipeline engine; CMOS process; Clocks; Computer architecture; Decoding; Engines; Memory management; Pipelines; Prefetching; Testing; Very large scale integration;
Conference_Titel :
Solid-State Circuits Conference, 1989. Digest of Technical Papers. 36th ISSCC., 1989 IEEE International
Conference_Location :
New York, NY, USA
DOI :
10.1109/ISSCC.1989.48187
