DocumentCode
3164427
Title
CMOS gate array implementation of SPARC
Author
Quach, Le ; Chueh, Richard
Author_Institution
Fujitsu Microelectron. Inc., Tokyo, Japan
fYear
1988
fDate
Feb. 29 1988-March 3 1988
Firstpage
14
Lastpage
17
Abstract
A description is given of the implementation of the 32-bit RISC (reduced-instruction-set-computer)-based SPARC (Scalable Processor Architecture) microprocessor chip set MB86900 and MB86910 using a CMOS 20K gate array to meet a tight development schedule while achieving high performance with high degree of testability. MB86900 is the CPU and MB86910 is the floating-point controller. Although these components were implemented in a gate array, the performance exceeds that of most of the existing commercial full-custom microprocessors.<>
Keywords
CMOS integrated circuits; microprocessor chips; reduced instruction set computing; 20K gate array; 32 bit; 32-bit RISC-based SPARC microprocessor chip set; CPU; MB86900; MB86910; development schedule; floating-point controller; Clocks; Databases; Microprocessor chips; Packaging; Processor scheduling; Reduced instruction set computing; Registers; Testing; Timing; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Compcon Spring '88. Thirty-Third IEEE Computer Society International Conference, Digest of Papers
Conference_Location
San Francisco, CA, USA
Print_ISBN
0-8186-0828-5
Type
conf
DOI
10.1109/CMPCON.1988.4819
Filename
4819
Link To Document