Title :
A design for concurrent error detections in FPLAs
Author :
Chang, Tsin-Yuan ; Hsu, Jean-Bean ; Wang, Cheng-Chi ; Lin, Yu-Shen
Author_Institution :
Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Abstract :
A combined design of four concurrent error detection (CED) schemes-the alternating logic scheme, duplication of the on-set scheme, duplication of the off-set scheme, and the parity checking scheme, is proposed for field programmable logic arrays (FPLAs) which inherently has unutilized elements. One of the four CED schemes can be implemented by the proposed circuit and the unutilized elements with the constraint that the unused elements can be programmed as parts of test logic
Keywords :
error detection; logic arrays; logic testing; alternating logic scheme; concurrent error detections; design; field programmable logic arrays; parity checking scheme; Circuit faults; Circuit synthesis; Circuit testing; Electrical fault detection; Fault detection; Logic circuits; Logic design; Logic testing; Pins; Programmable logic arrays;
Conference_Titel :
VLSI, 1992., Proceedings of the Second Great Lakes Symposium on
Conference_Location :
Kalamazoo, MI
Print_ISBN :
0-8186-2610-0
DOI :
10.1109/GLSV.1992.218371
