Title :
A 20 MIPS sustained 32 b CMOS microprocessor with 64 b data bus
Author :
Jouppi, N.P. ; Tang, J.Y.F. ; Dion, J.
Author_Institution :
Digital Equipment Corp., Palo Alto, CA, USA
Abstract :
The authors describe a full-custom 32-b microprocessor which uses a 1.5- mu m drawn n-well CMOS technology with single polycide and two levels of metal. The die size is 7.76 mm*6.21 mm and contains 180 k transistors, of which 150 k are used in the cache or register file. The CPU executes an RISC instruction set with simple and regular encoding. The chip has been designed for operation at 20 MIPS (million instructions per second), running large benchmarks in a complete system. Power dissipation at 25 degrees C with a 5-V supply is under 3 W. The chip has 136 signal, 16 power, and 16 ground pads and is packaged in a 176-pin plastic pin-grid-array package with eight decoupling capacitors. The CPU pipeline and machine organization and the instruction fetch pipestage are shown.<>
Keywords :
CMOS integrated circuits; VLSI; instruction sets; microprocessor chips; pipeline processing; reduced instruction set computing; 1.5 micron; 20 MIPS; 3 W; 32 bit; 5 V; 64 bit; CMOS microprocessor; CPU pipeline; RISC instruction set; VLSI; decoupling capacitors; double level metal; external data bus; full-custom; n-well CMOS technology; plastic pin-grid-array package; single polycide; CMOS technology; Capacitors; Encoding; Microprocessors; Packaging machines; Pipelines; Plastic packaging; Power dissipation; Reduced instruction set computing; Registers;
Conference_Titel :
Solid-State Circuits Conference, 1989. Digest of Technical Papers. 36th ISSCC., 1989 IEEE International
Conference_Location :
New York, NY, USA
DOI :
10.1109/ISSCC.1989.48192
