Title :
On the use of hierarchy in timing verification with statically sensitizable paths
Author :
Johannes, P. ; Claesen, L. ; De Man, H.
Author_Institution :
IMEC, Leuven, Belgium
Abstract :
A novel solution for the efficiency problems encountered in static timing verification is presented. The LSP algorithm is submitted to a critical analysis. A new hierarchy based approach is presented and its advantages and limitations are highlighted. Finally, some results on real life circuits are presented
Keywords :
VLSI; built-in self test; circuit analysis computing; LSP algorithm; VLSI circuits; hierarchy; statically sensitizable paths; timing verification; Algorithm design and analysis; Delay; Integrated circuit synthesis; Logic circuits; Performance analysis; Timing; Very large scale integration;
Conference_Titel :
VLSI, 1992., Proceedings of the Second Great Lakes Symposium on
Conference_Location :
Kalamazoo, MI
Print_ISBN :
0-8186-2610-0
DOI :
10.1109/GLSV.1992.218372
