A practical, flip-chip, multi-layer pre-encapsulation technology for wafer-scale underfill

This paper describes the conception, development, and application of a novel materials set and methodology for fabricating assembly-ready flip chips pre-encapsulated, at the wafer level, with a low coefficient of thermal expansion (CTE) underfill. This technology is unique in that it addresses a key challenge currently facing the high density interconnect (HDI) electronics industry-how to produce cost-effectively, in a streamlined process, reliably-underfilled flip chips on organic printed wiring board (PWB) substrates. Prior to the concept of multi-layer wafer-scale pre-encapsulation, the prevailing methods for underfilling of flip chips were either rapid-flow underfills, applied after assembly reflow, or no-flow underfills, applied prior to assembly and reflow. Both of these methods have limitations and issues that make them questionable as long term solutions to the underfill problem. The multi-layer pre-encapsulation technology addresses the important issues in electronics assembly: cost, impact on the current surface mount technology (SMT) assembly process, and reliability of flip chip assemblies produced. Success in addressing these issues will help flip chip technology, with its clear performance advantages over packaged die, achieve widespread applicability