Flip chip assembly process development, reliability assessment and process characterization for polymer stud grid array-chip scale package

Author

Paydenkar, Chetan S. ; Jefferson, Fred Gerard ; Baldwin, Daniel F.

Author_Institution

George W. Woodruff Sch. of Mech. Eng., Georgia Inst. of Technol., Atlanta, GA, USA

fYear

2001

fDate

2001

Firstpage

782

Lastpage

789

Abstract

The Polymer Stud Grid Array (PSGA) package is a new and unique type of area array chip scale package that shows significant advantages over conventional package configurations by virtue of its high potential for miniaturization and process cost saving potential. This paper focuses on two key elements of PSGA technology which are: 1) developing a high throughput flip chip assembly process technology for PSGA-CSP configurations using existing Surface Mount Technology (SMT); and 2) qualifying the reliability performance of flip chip PSGA packages. The flip chip interconnection system evaluated is eutectic lead-tin solder. Various flip chip strategies are screened based on underfill materials and associated flip chip process technology. The underfill materials selected for evaluation are no flow reflowable, fast flow snap cure encapsulants, and high performance underfill systems. This work discusses issues related to developing a robust-high through-put flip chip assembly process and presents preliminary reliability based on air-to-air thermal cycling (-55°C to 125°C) of the assembled PSGA Chip Scale Packages (CSPs)

Keywords

chip scale packaging; encapsulation; flip-chip devices; integrated circuit interconnections; integrated circuit reliability; microassembling; soldering; surface mount technology; -55 to 125 C; Pb-Sn; SMT; area array CSP; chip scale package; eutectic Pb-Sn solder; fast flow snap cure encapsulants; flip chip assembly process development; flip chip interconnection system; high throughput assembly process technology; polymer stud grid array CSP; process characterization; reliability assessment; reliability performance qualification; surface mount technology; thermal cycling; underfill materials; Adaptive arrays; Assembly; Bonding; Chip scale packaging; Costs; Electronic packaging thermal management; Flip chip; Polymers; Surface-mount technology; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Components and Technology Conference, 2001. Proceedings., 51st

Conference_Location

Orlando, FL

ISSN

0569-5503

Print_ISBN

0-7803-7038-4

Type

conf

DOI

10.1109/ECTC.2001.927869

Filename

927869