Flip chip assembly process development, reliability assessment and process characterization for polymer stud grid array-chip scale package

The Polymer Stud Grid Array (PSGA) package is a new and unique type of area array chip scale package that shows significant advantages over conventional package configurations by virtue of its high potential for miniaturization and process cost saving potential. This paper focuses on two key elements of PSGA technology which are: 1) developing a high throughput flip chip assembly process technology for PSGA-CSP configurations using existing Surface Mount Technology (SMT); and 2) qualifying the reliability performance of flip chip PSGA packages. The flip chip interconnection system evaluated is eutectic lead-tin solder. Various flip chip strategies are screened based on underfill materials and associated flip chip process technology. The underfill materials selected for evaluation are no flow reflowable, fast flow snap cure encapsulants, and high performance underfill systems. This work discusses issues related to developing a robust-high through-put flip chip assembly process and presents preliminary reliability based on air-to-air thermal cycling (-55°C to 125°C) of the assembled PSGA Chip Scale Packages (CSPs)