CMOS customer implementation of the SPARC architecture

Author

Namjoo, M. ; Abu-Nofal, F. ; Carmean, D. ; Chandramouli, R. ; Chang, Y. ; Goforth, J. ; Hsu, W. ; Iwamoto, R. ; Murphy, C. ; Naot, U. ; Parkin, M. ; Pendleton, J. ; Porter, C. ; Reaves, J. ; Reddy, R. ; Swan, G. ; Tinker, D. ; Tong, P. ; Yang, L.

Author_Institution

Sun Microsyst. Inc., Mountain View, CA, USA

fYear

1988

fDate

Feb. 29 1988-March 3 1988

Firstpage

18

Lastpage

20

Abstract

Using custom circuitry, a higher level of performance has been achieved for a new implementation of the Scalable Processor Architecture (SPARC). A CY601 processor (integer unit), running at a clock rate of 25-33 MHz, implements the complete set of SPARC instructions in a 0.8- mu m CMOS technology. An overview is given of the processor chip and its interface to the external cache, floating-point unit, and a generic coprocessor.<>

Keywords

CMOS integrated circuits; computer architecture; microprocessor chips; 0.8 micron; CMOS customer implementation; CY601 processor; SPARC architecture; Scalable Processor Architecture; floating-point unit; generic coprocessor; integer unit; Availability; Coprocessors; Decoding; Jamming; Pipelines; Prefetching; Programmable logic arrays; Registers; Signal processing; Sun;

fLanguage

English

Publisher

ieee

Conference_Titel

Compcon Spring '88. Thirty-Third IEEE Computer Society International Conference, Digest of Papers

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-8186-0828-5

Type

conf

DOI

10.1109/CMPCON.1988.4820

Filename

4820