DocumentCode :
3164751
Title :
A 70 MHz 32 b microprocessor with 1.0 mu m BiCMOS macrocell library
Author :
Hotta, T. ; Bandoh, T. ; Hotta, A. ; Nakano, T. ; Iwamoto, S. ; Adachi, S.
Author_Institution :
Hitachi Ltd., Japan
fYear :
1989
fDate :
15-17 Feb. 1989
Firstpage :
124
Lastpage :
125
Abstract :
A 70-MHz, 32-b microprocessor fabricated using BiCMOS macrocells is described. The chip contains about 529 k transistors, 521 k MOS transistors (98.5%), and 8 k bipolar transistors (1.5%). This small number of bipolar transistors increases the speed of the microprocessor chip to 70 MHz (40 MHz worst case), without increasing chip size. The macrocell design strategy is to increase integration density by using CMOS-based macrocells, reduce interchip communications, and accelerate the critical path by using bipolar drivers and sense circuits without increasing the total chip size. The BiCMOS device characteristics and chip specifications are given along with the macrocell specifications.<>
Keywords :
BIMOS integrated circuits; logic CAD; microprocessor chips; 1 micron; 32 bit; 70 MHz; BiCMOS macrocell library; CAD; CMOS-based macrocells; bipolar drivers; bipolar sense circuits; microprocessor; BiCMOS integrated circuits; CMOS logic circuits; Clocks; Libraries; Macrocell networks; Microprocessors; Read only memory; Registers; Solid state circuits; Synchronization;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference, 1989. Digest of Technical Papers. 36th ISSCC., 1989 IEEE International
Conference_Location :
New York, NY, USA
Type :
conf
DOI :
10.1109/ISSCC.1989.48205
Filename :
48205
Link To Document :
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