A 1 Mb flash EEPROM

Author

Cernea, R.-A. ; Samachisa, G. ; Su, C.-S. ; Tsai, H.-F. ; Kao, Y.-S. ; Wang, C.-Y.M. ; Chen, Y.-S. ; Renninger, A. ; Wong, T. ; Brennan, J., Jr. ; Haines, J.

Author_Institution

SEEQ Technol. Inc., San Jose, CA, USA

fYear

1989

fDate

15-17 Feb. 1989

Firstpage

138

Lastpage

139

Abstract

A 1-Mb flash EEPROM (electrically erasable and programmable read-only memory) with a 5.6- mu m*4.4- mu m cell is fabricated with a double-polysilicon, single-metal, n-well CMOS process. A double-diffused drain structure is used to reduce hot-electron degradation of n-channel peripheral devices. The memory is organized into 1024 rows and 128 columns for each output. Erase and programming operations are internally controlled by a timer that is stabilized against temperature and voltage supply variations. Addresses and data are latched during program and erase operations. Internal pumps generate the high voltage for the erase operation. Six redundant rows and two redundant columns are provided to enhance yield. Flash EEPROM cells similar to the array cells are used as the programmable elements in the redundancy circuits. Process parameters are given.<>

Keywords

CMOS integrated circuits; EPROM; integrated memory circuits; redundancy; 1 Mbit; 120 ns; double-diffused drain structure; double-polysilicon; electrically erasable; flash EEPROM; n-well CMOS process; programmable read-only memory; redundancy circuits; redundant columns; redundant rows; single-metal; CMOS process; CMOS technology; Circuit testing; Current supplies; Degradation; EPROM; Oscillators; Shift registers; Stress; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1989. Digest of Technical Papers. 36th ISSCC., 1989 IEEE International

Conference_Location

New York, NY, USA

Type

conf

DOI

10.1109/ISSCC.1989.48211

Filename

48211