Test quality improvement by physical testability enhancement

A methodology that provides a way to control the test quality of VLSI systems by predicting, diagnosing, and improving the IC defect coverage is presented for the case of the physical implementation of boundary scan circuitry, together with the software tools that implement it. The method allows the identification of hard-to-detect faults, their physical origin and layout location, leading to suggestions for design improvement by layout reconfiguration. The method is illustrated by the testability analysis of a full-custom design, implementing the boundary scan circuitry to be added to a core logic IC, in accordance with the IEEE P.1149 standard.<>