Title :
A multistep ADC family with efficient architecture
Author :
Chin, S. ; Mayes, M.K. ; Filippi, R.
Author_Institution :
Nat. Semicond. Corp., Santa Clara, CA, USA
Abstract :
A family of 8- and 10-bit A/D (analog/digital) converters has been developed using an efficient multistep architecture. The 10-bit A/D converter requires two 4-bit (two 3-bit for the 8-bit converter) flash cycles and a 3-bit voltage estimator. For the 10-bit converter, the architecture allows a reduction of comparator count to 16 and the resistor count to 96. While the conversion speed is similar to that of conventional half-flash A/D converters, power consumption and die size are lower due to the reduced number of components. The detailed operation of the A/D converter is illustrated, and a summary of test results is given.<>
Keywords :
analogue-digital conversion; digital integrated circuits; 10 bit; 3-bit voltage estimator; 8 bit; comparator count; conversion speed; die size; efficient architecture; flash cycles; multistep ADC family; power consumption; resistor count; Capacitors; Circuit testing; Decoding; Delay; Energy consumption; Heart; Phase estimation; Resistors; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 1989. Digest of Technical Papers. 36th ISSCC., 1989 IEEE International
Conference_Location :
New York, NY, USA
DOI :
10.1109/ISSCC.1989.48214
