A 36 kb/2 ns RAM with 1 kG/100 ps logic gate array

Author

Isomura, Satoru ; Uchida, A. ; Iwabuchi, M. ; Ogiue, K. ; Matsumura, K. ; Nakamura, T. ; Yamaguchi, K.

Author_Institution

Hitachi Ltd., Tokyo, Japan

fYear

1989

fDate

15-17 Feb. 1989

Firstpage

26

Lastpage

27

Abstract

An LSI device incorporating a 36-kb RAM and a 1k-gate logic array and using a 0.8- mu m sidewall base contact structure (SICOS) transistor process and four-layer metallization, is described. RAM and peripheral logic have been included in one chip to reduce input/output delay and interconnection delay between the RAM and logic. The chip layout is shown together with the circuit schematic of the RAM macro. RAM address access waveforms are shown along with the waveform of a 21-stage ring oscillator. Major device characteristics are summarized.<>

Keywords

MOS integrated circuits; digital integrated circuits; large scale integration; logic arrays; random-access storage; 0.8 micron; 100 ps; 2 ns; 21-stage ring oscillator; 36 kbit; LSI device; RAM address access waveforms; RAM macro; SICOS transistor process; chip layout; four-layer metallization; input/output delay; interconnection delay; logic gate array; peripheral logic; sidewall base contact structure; Clocks; Cutoff frequency; Driver circuits; Logic arrays; Logic devices; Logic gates; Macrocell networks; Power dissipation; Read-write memory; Space vector pulse width modulation;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1989. Digest of Technical Papers. 36th ISSCC., 1989 IEEE International

Conference_Location

New York, NY, USA

Type

conf

DOI

10.1109/ISSCC.1989.48218

Filename

48218