Title :
A 512 kb/5 ns BiCMOS RAM with 1 kG/150 ps logic gate array
Author :
Odaka, M. ; Nakamura, K. ; Eno, K. ; Ogiue, K. ; Saito, O. ; Ikeda, T. ; Hirao, M. ; Higuchi, H.
Author_Institution :
Hitachi Ltd., Tokyo, Japan
Abstract :
An ECL (emitter-coupled-logic) 512-kb BiCMOS SRAM (statistic random access memory) with 1-kG logic and using 0.8- mu m high-performance bipolar CMOS (Hi-BiCMOS) technology is described. The RAM has 5-ns address access time and 2-ns write-pulse width. The logic gate has 150-ps propagation delay with 4-mW power dissipation. A RAM-with-logic configuration is adopted to eliminate interconnection delay between the RAM and peripheral logic and to facilitate a wide-bit RAM. The design rule dependence of the delay time of a three-input ECL OR/NOR gate and a two-input BiCMOS NAND gate is shown. On-chip address access times, under 5 ns from address latches to data-out latches at room temperature with a marching test pattern, are also shown. Major characteristics of the LSI are presented.<>
Keywords :
BIMOS integrated circuits; digital integrated circuits; emitter-coupled logic; large scale integration; logic arrays; random-access storage; 0.8 micron; 150 ps; 4 mW; 5 ns; 512 kbit; ECL BiCMOS SRAM; LSI; RAM-with-logic configuration; address access time; delay time; design rule dependence; interconnection delay; logic gate array; power dissipation; propagation delay; statistic random access memory; three-input ECL OR/NOR gate; two-input BiCMOS NAND gate; wide-bit RAM; write-pulse width; BiCMOS integrated circuits; CMOS logic circuits; CMOS technology; Logic arrays; Logic gates; Power dissipation; Propagation delay; Random access memory; Read-write memory; Statistics;
Conference_Titel :
Solid-State Circuits Conference, 1989. Digest of Technical Papers. 36th ISSCC., 1989 IEEE International
Conference_Location :
New York, NY, USA
DOI :
10.1109/ISSCC.1989.48219
