Linearity Improvement of Doherty Amplifier with Analog Predistorter for WCDMA Applications

This paper presents a Doherty amplifier with analog predistorter for high linearity and efficiency. The predistortion technique is used to improve the linearity of the Doherty amplifier while preserving the high efficiency. The gate bias voltage of the peaking amplifier as well as the vector modulator in the predistorter is adjusted optimally at each output power level. For the experimental verification, a Doherty amplifier with analog predistorter is implemented using 30-W PEP LDMOSFETs and tested for four-carrier wideband code-division multiple access (WCDMA) applications. With the optimum gate bias voltage of the peaking amplifier, the adjacent channel leakage ratio (ACLR) and the drain efficiency are improved significantly at the wide output power levels. At an ACLR of -45 dBc, the output power and drain efficiency are 40.8 dBm and 37.8%, respectively