A 3.5 ns, 500 mW 16 kb BiCMOS ECL RAM

Author

Suzuki, M. ; Tachibana, S. ; Watanabe, A. ; Shukuri, S. ; Higuchi, H. ; Nagano, T. ; Shimohigashi, K.

Author_Institution

Hitachi Ltd., Tokyo, Japan

fYear

1989

fDate

15-17 Feb. 1989

Firstpage

32

Lastpage

33

Abstract

A 16-Kb RAM was designed and fabricated using a 0.5- mu m BiCMOS technology. It has a typical address access time of 3.5 ns. The RAM operates at a supply voltage of -4.5 V and features 500-mW power dissipation. A description is given of two techniques crucial to high-speed, low-power design: a wired -OR precoder combined with a low-power, high-speed level converter circuit and a direct column-sensing circuit with a cascode differential amplifier.<>

Keywords

BIMOS integrated circuits; emitter-coupled logic; integrated memory circuits; random-access storage; 0.5 micron; 16 kbit; 3.5 ns; 500 mW; BiCMOS ECL RAM; address access time; cascode differential amplifier; direct column-sensing circuit; high-speed level converter circuit; low-power design; power dissipation; wired -OR precoder; BiCMOS integrated circuits; Bipolar transistors; Capacitance; Delay effects; Differential amplifiers; Diodes; Electrodes; Laboratories; Power dissipation; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1989. Digest of Technical Papers. 36th ISSCC., 1989 IEEE International

Conference_Location

New York, NY, USA

Type

conf

DOI

10.1109/ISSCC.1989.48221

Filename

48221