A 9 ns 1 Mb CMOS SRAM

Author

Sasaki, K. ; Hanamura, S. ; Ishibashi, K. ; Yamanaka, T. ; Hashimoto, N. ; Nishida, T. ; Shimohigashi, K. ; Honjo, S.

Author_Institution

Hitachi Ltd., Tokyo, Japan

fYear

1989

fDate

15-17 Feb. 1989

Firstpage

34

Lastpage

35

Abstract

A 1-Mb (256k*4/1M*1) CMOS SRAM (static random access memory), fabricated using a half-micron triple-poly double-metal CMOS technology, is reported. A 9-ns access time is attained with 5-V supply and 30-pF load capacitance. This access time has been achieved with a three-stage pMOS cross-coupled sense amplifier, 0.6- mu m high-performance MOSFETs, and an optimized internal supply voltage scheme. A redundancy scheme with no access time penalty has been incorporated. The sense amplifier circuit combined with a CMOS cross-coupled preamplifier has under 10-ns access time. Address and data output waveforms are shown. Typical active current is 55 mA at 30 MHz, and typical standby current is 15 mA (TTL). Typical RAM characteristics are listed.<>

Keywords

CMOS integrated circuits; integrated memory circuits; random-access storage; 0.5 micron; 1 Mbit; 15 mA; 30 pF; 55 mA; 9 ns; CMOS SRAM; access time; active current; address output waveform; data output waveforms; high-performance MOSFETs; load capacitance; optimized internal supply voltage scheme; redundancy scheme; standby current; static random access memory; three-stage pMOS cross-coupled sense amplifier; triple-poly double-metal CMOS technology; CMOS technology; Capacitance; Coupling circuits; Error analysis; MOS devices; Mirrors; Pulse amplifiers; Random access memory; Redundancy; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1989. Digest of Technical Papers. 36th ISSCC., 1989 IEEE International

Conference_Location

New York, NY, USA

Type

conf

DOI

10.1109/ISSCC.1989.48222

Filename

48222