An 8 ns 1 Mb ECL BiCMOS SRAM

Author

Matsui, Masaki ; Momose, H. ; Urakawa, Y. ; Maeda, T. ; Suzuki, A. ; Urakawa, N. ; Sato, Kiminori ; Makita, Kikuo ; Matsunaga, J. ; Ochii, K.

Author_Institution

Toshiba Corp., Kawasaki, Japan

fYear

1989

fDate

15-17 Feb. 1989

Firstpage

38

Lastpage

39

Abstract

A description is given of a 1-Mb*1ECL (emitter-coupled-logic) SRAM (static random access memory) fabricated with a 0.8- mu m BiCMOS technology which has 8-ns access time and is 10K-I/O (input/output) compatible. To achieve sub-10 ns address access time and low power consumption, an ECL CMOS level converter, a bit-line peripheral circuit, and an automatic power saving function are employed. Details of the 0.8- mu m BiCMOS process technology are summarized, and an oscilloscope photograph shows 8-ns address access time under nominal conditions. The RAM characteristics are summarized.<>

Keywords

BIMOS integrated circuits; emitter-coupled logic; integrated memory circuits; random-access storage; 0.8 micron; 1 Mbit; 8 ns; BiCMOS ECL SRAM; ECL CMOS level converter; I/O compatibility; access time; automatic power saving function; bit-line peripheral circuit; low power consumption; oscilloscope photograph; BiCMOS integrated circuits; Delay; Energy consumption; Laboratories; Pulse amplifiers; Random access memory; Read-write memory; Semiconductor devices; Solid state circuits; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1989. Digest of Technical Papers. 36th ISSCC., 1989 IEEE International

Conference_Location

New York, NY, USA

Type

conf

DOI

10.1109/ISSCC.1989.48224

Filename

48224