Title :
A 20 ns 1 Mb CMOS burst mode EPROM
Author :
Ashmore, B. ; Schreck, J. ; Truong, P. ; Coffman, T. ; Andrews, M.
Author_Institution :
Texas Instrum. Inc., Houston, TX, USA
Abstract :
A 64-K*16-b burst-mode EPROM (electrically programmable read-only memory) with a 20-ns statistical access time was achieved using 1.4- mu m lithography. An orthogonal x-drive and split array architecture allows efficient array segmentation utilizing a contactless buried diffusion memory cell. The resultant die size is 54.6 mm/sup 2/. The contactless, buried-diffusion memory cell is constructed using a self-aligned thick oxide (SATO) process which minimizes the array dimensions by requiring diffusion contacts only every 16 bits. The SATO array can be continuously biased without a power penalty because of its virtual ground array configuration. In many system applications, the burst mode memory configuration offers performance approaching maximum processor capability.<>
Keywords :
CMOS integrated circuits; EPROM; integrated memory circuits; memory architecture; 1 Mbit; 1.4 micron; 20 ns; CMOS burst mode EPROM; SATO array; array segmentation; contactless buried diffusion memory cell; die size; lithography; orthogonal x-drive; self-aligned thick oxide; split array architecture; statistical access time; virtual ground array configuration; CMOS technology; Decoding; Dielectrics; Driver circuits; EPROM; Silicides; Solid state circuits;
Conference_Titel :
Solid-State Circuits Conference, 1989. Digest of Technical Papers. 36th ISSCC., 1989 IEEE International
Conference_Location :
New York, NY, USA
DOI :
10.1109/ISSCC.1989.48225
