Title :
VLSI architectures for video signal processing
Author :
Pirsch, Peter ; Gehrke, Winfried
Author_Institution :
Hannover Univ., Germany
Abstract :
The paper presents an overview on architectures for VLSI implementations of video compression schemes as specified by standardization committees of the ITU and ISO, focussing on programmable architectures. Programmable video signal processors are classified and specified as homogeneous and heterogeneous processor architectures. Heterogeneous processors outperform homogeneous processors due to adaptation to the requirements of special subtasks by dedicated modules. The majority of heterogeneous processors incorporate dedicated modules for high performance subtasks of high regularity like DCT and block matching. By normalization to a fictive 1.0 micron CMOS process typical linear relationships between silicon area and throughput rate have been determined for the different architectural styles. This relationship indicates a figure of merit for silicon efficiency
Keywords :
CMOS digital integrated circuits; VLSI; data compression; digital signal processing chips; discrete cosine transforms; image matching; modules; parallel architectures; telecommunication standards; video codecs; video coding; 1.0 micron; CMOS process; DCT; ISO; ITU; Si efficiency; VLSI architectures; block matching; dedicated modules; heterogeneous processor architectures; homogeneous processor architectures; linear relationships; normalization; programmable architectures; programmable video signal processors; standardization committees; subtasks; throughput rate; video compression schemes; video signal processing;
Conference_Titel :
Image Processing and its Applications, 1995., Fifth International Conference on
Conference_Location :
Edinburgh
Print_ISBN :
0-85296-642-3
DOI :
10.1049/cp:19950609
