A 90 ns 100 K erase/program cycle megabit flash memory

An electrically erasable, reprogrammable, 90-ns 1-Mb flash memory capable of greater than 100000 erase/program cycles is described. The memory implements a command port and an internal reference voltage generator, allowing microprocessor-controlled reprogramming. The 90-ns access time results from the 95- mu A memory cell current, low resistance polysilicide word lines, advanced scaled periphery transistors, and a di/dt optimized data-out buffer. Using CMOS inputs, power dissipation is 40 mW in the active state and 20 mu W in standby. The memory electrically erases in 900 ms and programs at the rate of 10 mu s/byte. The device contains thirty-two columns of redundant elements and utilizes flash memory cells to store the address of repaired columns. The memory was fabricated on a 1- mu m double-poly n-well CMOS process. A typical cell erase/program V/sub t/ margin is shown as a function of the number of reprogramming cycles. After 100000 cycles there is still a 2.5-V program-read margin to ensure data retention. Device parameters are listed.<>