Flip chip in leaded molded package (FLMP)

In the semiconductor industry, reducing the size of power electronics has been limited by the thermal performance of miniature surface mount packages. A key development in the industry has been the availability of more efficient silicon, allowing a lower on resistance die (RDS(ON)) to fit in a smaller package. However new innovative surface mount packages such as the MOSFET BGA package which combine the small form factors of miniature packages with the thermal performance of much larger packages have been developed. These new packages have the added advantage of virtually eliminating the package resistance. However packages which involve the BGA form factor require different handling equipment as compared to leaded surface mount devices, slowing their adoption rate. In the flip chip in a leaded molded package (FLMP), these shortcomings have been addressed preserving the advantages of miniature packages such as the MOSFET BGA package. A die up to 75% larger in area as compared to its wire bonded counterpart with estimated θjc of <0.5°C/W are typical characteristics of this package. Packages of a low profile (<1.0 mm height) can also be easily constructed due to the absence of wire bonds. In addition, the construction of the package lends itself well to a “lead free” or a green package. The paper will describe the construction of the package, the process flow, the performance and early reliability results