DocumentCode :
3165716
Title :
Electrical test strategies for a wafer-level batch packaging technology
Author :
Keezer, D.C. ; Patel, C.S. ; Zhou, Q. ; Meindl, J.D.
Author_Institution :
Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
fYear :
2001
fDate :
2001
Firstpage :
1019
Lastpage :
1023
Abstract :
A wafer-level batch packaging (WLBP) technology is under development that provides compliant electrical leads with a density as high as 12,000 per cm2. The leads are processed while the integrated circuits are still in wafer form through a series of relatively simple photolithographic steps. After electrical testing, the wafers are diced and the ICs are ready for direct assembly to an interconnect substrate. Sufficient lateral and vertical compliance is provided by the leads to accommodate the non-planarity encountered during assembly and thermal mismatch between the IC and substrate during normal operation. The high density of leads presents both challenges and opportunities for electrical testing. This paper summarizes the process technology used to fabricate these high-density electrical contacts. Several potential test strategies are introduced that may take advantage of these contacts
Keywords :
electrical contacts; integrated circuit interconnections; integrated circuit packaging; integrated circuit testing; photolithography; assembly process; compliant electrical lead; electrical testing; high-density electrical contact; integrated circuit; interconnect substrate; photolithography; thermal mismatch; wafer-level batch packaging technology; Assembly; Bonding; Circuit testing; Contacts; Fabrication; Integrated circuit packaging; Integrated circuit technology; Lead; Probes; Wafer scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Components and Technology Conference, 2001. Proceedings., 51st
Conference_Location :
Orlando, FL
ISSN :
0569-5503
Print_ISBN :
0-7803-7038-4
Type :
conf
DOI :
10.1109/ECTC.2001.927936
Filename :
927936
Link To Document :
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