A single-chip digital signaling interface for the DSI intraoffice environment

A single-chip data transceiver meeting the DSI (Digital Signaling Interface) (1.544 Mb/s) intraoffice requirements is presented. The DSI provides receive-pulse regeneration, timing recovery, and transmit-pulse rate pre-equalization along with alarm and status monitoring for a four-wire, full-duplex communication link over twisted pair. It contains a transmit driver circuit which reduces chip power consumption to 115 mW, about one third the power of existing devices. A monolithic clock multiplier circuit creates internal chip timing edges at 4*1.544 MHz, obviating the need for an external crystal-based timing reference. A data-latching circuit is used in the receive phase-locked loop (PLL) to improve input jitter accommodation. The DSI, designed in a 1.75- mu m CMOS process, occupies 20 mm/sup 2/ of silicon and operates from a 5-V (+or-10%) supply from a -40 to +85 degrees C.<>