Title :
Distributed circuit simulation using waveform relaxation in a slotted-ring architecture
Author :
Pon, Carlos R. ; Saleh, Resve ; Kwasniewski, Tad
Author_Institution :
Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada
Abstract :
A distributed event-driven waveform relaxation (WR) algorithm is presented, which has been mapped on to a slotted-ring parallel architecture, to accelerate the circuit simulation problem at the electrical level. The simulator was adopted from a portable simulator developed at the University of Illinois. A message-passing paradigm was build around it to simulate circuits in a distributed manner. A speedup factor between 1.4 to 3.4 were obtained, using 4 processing elements (PEs)
Keywords :
VLSI; circuit analysis computing; distributed algorithms; iterative methods; message passing; parallel architectures; University of Illinois; VLSI circuits; algorithm; distributed circuit simulation; distributed event-driven waveform relaxation; message-passing paradigm; portable simulator; processing elements; slotted-ring parallel architecture; speedup factor; Circuit simulation; Distributed computing; Iterative methods; Parallel architectures; Very-large-scale integration;
Conference_Titel :
Electrical and Computer Engineering, 1994. Conference Proceedings. 1994 Canadian Conference on
Conference_Location :
Halifax, NS
Print_ISBN :
0-7803-2416-1
DOI :
10.1109/CCECE.1994.405809
