A hierarchical memory structure for the 3D shelling technique

The authors earlier proposed a new space partitioning for mapping computations of the radiosity method onto a highly pipelined parallel architecture (L.S. Shen et al., 1990; 1991). This shelling technique can alleviate the communication load between the host and the processors in a shared-memory architecture, but the system performance might deteriorate when increasing the number of processors. A memory structure which is a hierarchy of resident set, cache, and main memory is presented. It can reduce the average access time of a patch and thus provide better balancing between processing throughput and memory bandwidth, to enhance the pipelinability of computations. A method of selecting the resident set is described, and different policies in the cache design are investigated.<>