DocumentCode
3166842
Title
Extending dual stress liner process to high performance 32nm node SOI CMOS manufacturing
Author
Cai, M. ; Greene, B.J. ; Strane, J. ; Belyansky, M. ; Tamweber, F. ; Lee, D. ; van Meer, H. ; Laffosse, E. ; Luning, S. ; Mocuta, D. ; Maciejewski, E.
Author_Institution
IBM Syst.&Technol. Group, Hopewell Junction, NY
fYear
2008
fDate
6-9 Oct. 2008
Firstpage
17
Lastpage
18
Abstract
Dual stress liner process for high performance SOI CMOS technology at 32 nm technology node is improved through the use of dep-etch-dep, etch back, and spacer removal techniques. The stress benefit of DSL is preserved with improved gap fill for the manufacturing of sub-32 nm gate length transistors.
Keywords
CMOS analogue integrated circuits; insulated gate field effect transistors; silicon-on-insulator; SOI CMOS technology; dep-etch-dep technique; dual stress liner process; etch back technique; size 32 nm; spacer removal techniques; sub-32nm gate length transistors; CMOS process; CMOS technology; Compressive stress; Conference proceedings; DSL; Etching; Manufacturing processes; Semiconductor device manufacture; Space technology; Tensile stress;
fLanguage
English
Publisher
ieee
Conference_Titel
SOI Conference, 2008. SOI. IEEE International
Conference_Location
New Paltz, NY
ISSN
1078-621X
Print_ISBN
978-1-4244-1954-8
Electronic_ISBN
1078-621X
Type
conf
DOI
10.1109/SOI.2008.4656273
Filename
4656273
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