Author :
La Tulipe, D.C., Jr. ; Frnak, D.J. ; Steen, S.E. ; Topol, A.W. ; Patel, J. ; Ramakrishnan, L. ; Sleight, J.W.
Author_Institution :
IBM T. J. Watson Res. Center, Yorktown Heights, NY
Abstract :
To address key challenges in transistor scaling [1,2], we have used 3D oxide bonding technology in a new way, to fabricate CMOS devices and circuits in which the gate is on the opposite side of the channel from the contacts between the FET and the first wiring level (Ml).
Keywords :
CMOS integrated circuits; bonding processes; capacitance; field effect transistors; semiconductor device models; silicon-on-insulator; 3D oxide bonding technology; 3D processing technique; CMOS circuits; PDSOI devices; UFET design; parasitic drain-to-gate capacitance; transistor scaling; Conference proceedings; Decision support systems; FETs; Fiber reinforced plastics; Quadratic programming; Virtual reality;
Conference_Titel :
SOI Conference, 2008. SOI. IEEE International
Conference_Location :
New Paltz, NY
Print_ISBN :
978-1-4244-1954-8
Electronic_ISBN :
1078-621X
DOI :
10.1109/SOI.2008.4656276
