Title :
A low-power CMOS power amplifier for IEEE 802.11a applications
Author :
Kang, Jyun-Jie ; Weng, Ro-Min ; Liu, Chun-Yu
Author_Institution :
Dept. of Electr. Eng., Nat. Dong Hwa Univ., Hualien, Taiwan
Abstract :
A low-power fully-integrated power amplifier (PA) for IEEE 802.11a applications is designed with 0.18 ¿m radio frequency CMOS process. A folded cascode structure is adopted to reduce the supply voltage. The driver stage acts as a preamplifier which is composed of an inverse amplifier with a gate-driving circuit. The peak power-added efficiency (PAE) is 24.5% at 3 V supply voltage. The output 1 dB compression point OP1dB is 20.5 dBm. The saturated output power achieves 21.8 dBm at 5.2 GHz. The biasing current of 114 mA and 167 mA are consumed at quiescent point and P1dB, respectively. The power gain within the linear operating range is 20.3 dB. The maximum output power is 21 dBm. The maximum PAE is 24.5%.
Keywords :
CMOS integrated circuits; power amplifiers; wireless LAN; IEEE 802.11 applications; current 114 mA; current 167 mA; folded cascode structure; frequency 5.2 GHz; gate-driving circuit; inverse amplifier; low-power CMOS power amplifier; peak power-added efficiency; preamplifier; quiescent point; radiofrequency CMOS process; size 0.18 mum; voltage 3 V; wireless local area networks; Bandwidth; Circuits; Frequency conversion; Laboratories; Magnetic analysis; Optimization methods; Planar waveguides; Power dividers; Rectangular waveguides; Transducers; Power amplifier; low power;
Conference_Titel :
Microwave Conference, 2009. APMC 2009. Asia Pacific
Conference_Location :
Singapore
Print_ISBN :
978-1-4244-2801-4
Electronic_ISBN :
978-1-4244-2802-1
DOI :
10.1109/APMC.2009.5384351
