• DocumentCode
    3166983
  • Title

    Array architecture of floating body cell (FBC) with quasi-shielded open bit line scheme for sub-40nm node

  • Author

    Fujita, Katsuyuki ; Ohsawa, Takashi ; Fukuda, Ryo ; Matsuoka, Fumiyoshi ; Higashi, Tomoki ; Shino, Tomoaki ; Watanabe, Yohji

  • Author_Institution
    Center for Semicond. R&D, Toshiba Corp. Semicond. Co., Yokohama
  • fYear
    2008
  • fDate
    6-9 Oct. 2008
  • Firstpage
    31
  • Lastpage
    32
  • Abstract
    Cell array architecture for floating body RAM of 35 nm bit line half pitch is described. The quasi-non-destructive-read-out feature of floating body cell contributes to eliminating inter-bit line coupling noise in open bit line architecture without degrading the cycle time of the RAM.
  • Keywords
    DRAM chips; circuit noise; nondestructive readout; DRAM chips; RAM; cell array architecture; floating body cell; inter-bit line coupling noise; quasinondestructive-read-out; quasishielded open bit line scheme; size 35 nm; size 40 nm; Capacitance; Charge pumps; Conference proceedings; Crosstalk; Noise cancellation; Random access memory; Read-write memory; Research and development; Tin; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    SOI Conference, 2008. SOI. IEEE International
  • Conference_Location
    New Paltz, NY
  • ISSN
    1078-621X
  • Print_ISBN
    978-1-4244-1954-8
  • Electronic_ISBN
    1078-621X
  • Type

    conf

  • DOI
    10.1109/SOI.2008.4656280
  • Filename
    4656280
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3166983