Title :
A digital video signal processor for color image sensors
Author :
D´Luna, L.J. ; Parulski, K.A. ; Kenney, T.J. ; Hibbard, R.H. ; Guidash, R.M. ; Shelley, P.R. ; Cook, W.A. ; Brown, G.W. ; Tredwell, T.J.
Author_Institution :
Eastman Kodak Co., Rochester, NY, USA
Abstract :
The authors describe signal processor (DSP) for CCD (charge-coupled-device) cameras using a specified color filter array pattern. A block diagram of the DSP chip is shown. The chip has been designed and fabricated in a 2- mu m single-poly double-metal CMOS process. Eight scan-test registers were used at selected points in the processing chain to enable the entire chip to be tested, including ROMs and line delays, with 16 k vectors. The chip is functional at a maximum clock rate of 14.3 MHz. An image processed by the device is shown. The data path is designed with simple ripple-carry adders and dynamic registers. The on-chip programmable delay lines and 14.3-MHz clock-rate allow the chip to accommodate sensors for up to 768 active pixels, making it suitable for NTSC, CCIR 601 and PAL video standards.<>
Keywords :
CCD image sensors; CMOS integrated circuits; computerised picture processing; digital signal processing chips; video cameras; video signals; 14.3 MHz; 2 micron; 768 pixel; CCD cameras; CCIR 601; DSP chip; NTSC; PAL video standards; ROMs; charge-coupled-device; color filter array pattern; color image sensors; digital video signal processor; dynamic registers; line delays; maximum clock rate; on-chip programmable delay lines; ripple-carry adders; scan-test registers; signal processor; single-poly double-metal CMOS process; Charge coupled devices; Charge-coupled image sensors; Clocks; Color; Delay lines; Digital signal processing chips; Filters; Image sensors; Registers; Signal processing;
Conference_Titel :
Solid-State Circuits Conference, 1989. Digest of Technical Papers. 36th ISSCC., 1989 IEEE International
Conference_Location :
New York, NY, USA
DOI :
10.1109/ISSCC.1989.48240
