Electrical performance of compliant wafer level package

As the demand for portable and high speed communication products grows, wafer level packages with high chip-to-chip bandwidth and low package parasitics are required. A Compliant Wafer Level Package (CWLP) technology has been developed to meet the growing demand of higher electrical performance at low cost. The electrical performance of the compliant wafer level package in terms of its package parasitics and chip-to-chip bandwidth is investigated in this paper