A codec LSI for HDTV signals

The authors describe a codec LSI for a time-compressed-integration (TCI-) format high-definition TV (HDTV) signal. The chip converts a luminance signal sampled at 48.6 MHz and two chrominance signals sampled at 12.15 MHz into a TCI format signal at 48.6-MHz frequency and vice versa. The LSI employs a codec architecture to be used as a TCI encoder or decoder in one chip with minimum hardware and contains a PLL (phase-locked-loop) control circuit for clock synchronization in the decoder mode. It has three modes of operation corresponding to three HDTV systems, namely an analog transmission system, a 400-Mb/s digital transmission system, and a video disk player. The PLL control circuit executes a specific operation in each mode. The 48.6-MHz TCI or Y-signal is divided into two 24.3-MHz signals and applied to the LSI, thus allowing TTL (transistor-transistor logic) ICs to be used for the peripheral circuits. The chip was fabricated with a 1.2- mu m p-well CMOS and double-level Al interconnection technology. About 288 k elements, including a 52-kbit 1-Tr DRAM, are integrated in a 12.16-mm*12.10-mm die, mounted in a 209-pin pin-grid-array package.<>