An architecture for tree search based vector quantization for single chip implementation

Vector quantization (VQ) has become feasible for use in real-time applications by employing VLSI technology. The authors propose a new search algorithm and an architecture for implementing it, which can be used in real-time image processing. This search algorithm takes O (k) time units on a sequential machine, where k is the dimension of the codevectors, assuming unit time corresponds to one comparison operation. The proposed architecture employs a single processing element (PE) and O(N) external memory for storing N hyperplanes used in the search, where N is the number of codevectors. Compared with known architectures for VQ in the literature, the proposed design does not perform any multiplication operation, since the search method is independent of any L_q metric, 1⩽q⩽∞. It leads to an area efficient design with the PE consisting of a comparator and O(k) registers. Also, the memory used by the design is significantly less than those employed in the known architectures