Double-Gate Sub-32nm CMOS SRAM current and voltage sense amplifiers, insensitive to process variations and transistor mismatch

This paper describes two novel sub-32 nm current (CSA) and voltage (VSA) sense amplifiers in fully depleted (FD) double-gate (DG) silicon-on-insulator (SOI) technology with planar independent self-aligned gates. The proposed sense amplifiers (SA) need 40% to 4 times less power, achieve a 10-15% increase in speed and have a 2.5 to 3.5 times larger tolerance to Vth and L mismatch compared to published DG SAs. Both architectures take advantage of the back gate in order to improve circuit properties. The new CSA is by 12% faster and reduces power consumption 3.3 times compared to the new VSA, with the latter having a significant advantage in size.