Title :
Some low power implementations of DSP algorithms
Author :
Evans, Joseph B. ; Liu, Bede
Author_Institution :
Dept. of Electr. & Comput. Eng., Kansas Univ., Lawrence, KS, USA
Abstract :
The implementation of digital signal processing algorithms often requires that a variety of conflicting criteria be satisfied. A signal processing system must provide the necessary processing gains, while various measures of the feasibility and efficiency of implementation, such as power and cost, are met. This paper reviews the motivation behind the development of low power signal processing algorithms, presents some methods for addressing these problems, and gives several examples of reduced complexity signal processing implementations
Keywords :
computational complexity; digital signal processing chips; parallel algorithms; signal processing; DSP algorithms; digital signal processing algorithms; low power implementations; processing gains; reduced complexity; Adaptive filters; Analytical models; Arithmetic; Array signal processing; Computational modeling; Costs; Digital signal processing; Finite impulse response filter; Signal processing; Signal processing algorithms;
Conference_Titel :
Application Specific Array Processors, 1992. Proceedings of the International Conference on
Conference_Location :
Berkeley, CA
Print_ISBN :
0-8186-2967-3
DOI :
10.1109/ASAP.1992.218566