Checking formal specifications under simulation

“Verification” of large multiprocessor designs currently heavily on simulation. Formal techniques such as model checking are typically only applied to small parts of the system, due to issues of computational and notational complexity. With these two facts in mind the authors have designed a platform which aims to help bridge the gap between formal verification and simulation. They present a temporal logic specification language which includes constructs for specifying system behavior at a high level of abstraction, and discuss its use in simulation and model checking