Title :
A realtime image processing chip set
Author :
Eberhard, G. ; Groeneveld, H. ; Schneider, O. ; Simons, P.
Author_Institution :
Siemens AG, Munich, West Germany
Abstract :
A chip set is described which meets the requirements of calculation-intensive image processing algorithm (e.g. correlation) for real-time execution. It calculates one million two-dimensional correlation coefficients per second on a 16*16 pixel image at 25 MHz with a 6-b input resolution. The set consists of two chips, a multiplier-accumulator unit (MAC) and an arithmetic processing unit (APU). The MAC processes image data of different formats, up to 32 by 32 pixels, with a 6- or 12-b resolution, and outputs sums of products in an 18- or 36-b integer format. The APU converts these sums to a single-precision floating-point format (the internal data format) and calculates the correlation coefficient in 1- mu s with floating-point precision using the standard formula. A system configuration with both chips, a host processor, and input/output components is shown. The chip characteristics are summarized, and chip micrographs are shown.<>
Keywords :
CMOS integrated circuits; computerised picture processing; digital signal processing chips; real-time systems; 1.5 micron; 1024 pixel; 16 pixel; 25 MHz; 256 pixel; 32 pixel; DSP; arithmetic processing unit; calculation intensive algorithms; correlation; double metal 1.5 mu m CMOS process; image processing chip set; multiplier-accumulator unit; real-time execution; single-precision floating-point format; Arithmetic; CMOS integrated circuits; CMOS process; Image converters; Image processing; Image resolution; Logic; Pixel; Programmable control; Read only memory;
Conference_Titel :
Solid-State Circuits Conference, 1989. Digest of Technical Papers. 36th ISSCC., 1989 IEEE International
Conference_Location :
New York, NY, USA
DOI :
10.1109/ISSCC.1989.48242
