Title :
Discrete wavelet transforms in VLSI
Author :
Vishwanath, Mohan ; Owens, Robert M. ; Irwin, Mary Jane
Author_Institution :
Dept. of Comput. Sci., Pennsylvania State Univ., University Park, PA, USA
Abstract :
Three architectures, based on linear systolic arrays, for computing the discrete wavelet transform, are described. The AT 2 lower bound for computing the DWT in a systolic model is derived and shown to be AT2=Ω(N2 Nwk). Two of the architectures are within a factor of log N from optimal, but they are of practical importance due to their regular structure, scalability and limited I/O needs. The third architecture is optimal, but it requires complex control
Keywords :
VLSI; fast Fourier transforms; systolic arrays; AT2 lower bound; VLSI; complex control; discrete wavelet transforms; linear systolic arrays; scalability; systolic model; Computer architecture; Computer science; Convolution; Discrete wavelet transforms; Filters; Frequency; Optimal control; Scalability; Systolic arrays; Very large scale integration;
Conference_Titel :
Application Specific Array Processors, 1992. Proceedings of the International Conference on
Conference_Location :
Berkeley, CA
Print_ISBN :
0-8186-2967-3
DOI :
10.1109/ASAP.1992.218570
