DocumentCode
3167638
Title
Impact of layout style and parasitic capacitances in full adder
Author
Kamel, Dina ; Bol, David ; Flandre, Denis
Author_Institution
Microelectron. Lab., Univ. Catholique de Louvain, Louvain-la Neuve
fYear
2008
fDate
6-9 Oct. 2008
Firstpage
97
Lastpage
98
Abstract
This paper presents the impact of varying both the architecture and the technology on the performance of the full adder. A 10% reduction in total power and 15.2% reduction in delay are gained by changing the architecture. While an average power reduction of 15.5% and 14.1% reduction in average delay are gained by using SOI layout and junction capacitances instead of bulk.
Keywords
adders; capacitance; circuit layout; silicon-on-insulator; SOI layout; full adder; parasitic capacitance; power consumption; Adders; Appropriate technology; CMOS technology; Conference proceedings; Delay; Energy consumption; Inverters; MOS devices; Microelectronics; Parasitic capacitance;
fLanguage
English
Publisher
ieee
Conference_Titel
SOI Conference, 2008. SOI. IEEE International
Conference_Location
New Paltz, NY
ISSN
1078-621X
Print_ISBN
978-1-4244-1954-8
Electronic_ISBN
1078-621X
Type
conf
DOI
10.1109/SOI.2008.4656312
Filename
4656312
Link To Document