DocumentCode
3167765
Title
Characterization of a three-dimensional SOI integrated-circuit technology
Author
Chen, C.K. ; Checka, N. ; Tyrrell, B.M. ; Chen, C.L. ; Wyatt, P.W. ; Yost, D.R.W. ; Knecht, J.M. ; Kedzierski, J.T. ; Keast, C.L.
Author_Institution
Lincoln Lab., Massachusetts Inst. of Technol., Lexington, MA
fYear
2008
fDate
6-9 Oct. 2008
Firstpage
109
Lastpage
110
Abstract
This paper describe the process and test results after single tier circuit fabrication as well as after three-tier integration, determine impact of 3D vias on ring oscillator performance, and demonstrate functionality of single and multi-tier circuits of varying complexity.
Keywords
integrated circuit design; integrated circuit metallisation; integrated circuit technology; integrated circuit testing; monolithic integrated circuits; oscillators; silicon-on-insulator; 3D SOI integrated-circuit technology; Si; integrated circuit design; integrated circuit test; interconnect-metal layers; monolithically integrated 3D circuits; ring oscillator; tier circuit fabrication; Circuit testing; Delay; Fabrication; Finite impulse response filter; Integrated circuit interconnections; Integrated circuit technology; Inverters; Laboratories; Radio frequency; Random access memory;
fLanguage
English
Publisher
ieee
Conference_Titel
SOI Conference, 2008. SOI. IEEE International
Conference_Location
New Paltz, NY
ISSN
1078-621X
Print_ISBN
978-1-4244-1954-8
Electronic_ISBN
1078-621X
Type
conf
DOI
10.1109/SOI.2008.4656318
Filename
4656318
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