Title :
A low power CMOS LNA for 1–10GHz application
Author :
Hsu, Meng-Ting ; Hsu, Shih-Yu
Author_Institution :
Dept. & Inst. of Electron. Eng., Nat. Yunlin Univ. of Sci. & Technol., Douliou, Taiwan
Abstract :
This paper presents a 1-10 GHz low power and low noise amplifier (LNA) with resistive-feedback configuration. The design consists of two resistive-feedback amplifier. In order to reduce the chip area, resistive-feedback inverter is adopt for input matching. The output stage adopt basic topology of a resistive feedback for output matching, and add two inductor for inductive peaking at high-band. The implemented LNA shows a peak gain of 10.5 dB, the input reflection coefficient S11 lower than -8 dB and output reflection S22 are lower than -10.8 dB, and NF of 4.2~5.2 dB between 1~10 GHz while consuming 12.65 mw through a 1.5 V supply. The chip was fabricated in TSMC 0.18 um CMOS process.
Keywords :
CMOS integrated circuits; UHF amplifiers; low noise amplifiers; microwave amplifiers; frequency 1 GHz to 10 GHz; gain 10.5 dB; inductive peaking; low noise amplifier; low-power CMOS LNA; noise figure 4.2 dB to 5.2 dB; output matching; power 12.65 mW; resistive-feedback amplifier; resistive-feedback inverter; size 0.18 mum; voltage 1.5 V; CMOS process; Gain; Impedance matching; Inductors; Inverters; Low-noise amplifiers; Noise measurement; Output feedback; Reflection; Topology; low noise amplifier (LNA); low power; resistive-feedback;
Conference_Titel :
Microwave Conference, 2009. APMC 2009. Asia Pacific
Conference_Location :
Singapore
Print_ISBN :
978-1-4244-2801-4
Electronic_ISBN :
978-1-4244-2802-1
DOI :
10.1109/APMC.2009.5384397
