A precise sample-and-hold circuit topology in CMOS for low voltage applications with offset voltage self correction

Author

Ferreira, Carla ; Moreno, Robson L. ; Pimenta, Tales C. ; Filho, C.A.R.

Volume

2

fYear

2002

fDate

29 June-1 July 2002

Firstpage

914

Abstract

This work describes a new topology for CMOS sample-and-hold circuits in low voltage with self-correction of the offset voltage caused by mismatches in the differential input pair of the operational amplifier. The charge injection of the NMOS switches, although not properly modeled by the simulators, is an important factor and it is minimized in this topology. The results were obtained using the ACCUSIM II simulator on the AMS CMOS 0.8 μm CYE and they reveal the circuit has a reduced error of just 0.03% at the output.

Keywords

CMOS analogue integrated circuits; charge injection; circuit simulation; differential amplifiers; integrated circuit design; integrated circuit modelling; low-power electronics; network topology; operational amplifiers; sample and hold circuits; 0.8 micron; 100 kHz; 12 bit; NMOS switch charge injection; low voltage CMOS sample-and-hold IC; offset voltage self correction; operational amplifier differential input pair mismatch; output error reduction; precision sample-and-hold circuit topology; Capacitors; Circuit simulation; Circuit topology; Low voltage; MOS devices; Operational amplifiers; Sampling methods; Semiconductor device modeling; Switches; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications, Circuits and Systems and West Sino Expositions, IEEE 2002 International Conference on

Print_ISBN

0-7803-7547-5

Type

conf

DOI

10.1109/ICCCAS.2002.1178936

Filename

1178936