LP-HP nanoscale FinFET-CMOS design via source/drain engineering

An approach to nanoscale DG FinFET design for LP and HP nanoscale-CMOS applications via S/D engineering [i.e., control of N_SD(y)] was proposed, and demonstrated to be viable by device simulations and measurements. The approach exploits the idea of allowing S/D dopants properly distributed in the channel for HP-V_t design. We demonstrated the design approach at the 45nm node. Scaling L_g to Lt10nm, as projected at the end of the SIA roadmap [1], will require sigma_L to be reduced by about a factor of two, which appears feasible with acceptable sensitivities via new processing such as laser annealing.