Title :
High-speed 12 bit A/D converter
Author :
Zhang, Zhengfan ; Zhang, Jiabin ; Fan, Lin ; Shu, Huiran ; Li, Zhaoji
Author_Institution :
Univ. of Electron. Sci. & Technol. of China, Chengdu, China
fDate :
29 June-1 July 2002
Abstract :
A folding-interpolating, two-step conversion 12 bit CMOS analog-to-digital converter was designed in this paper. The folding-interpolating architecture adopts the dummy and the average technology, with coarse and fine bit correction. The differential nonlinearity error of the converter is less than ±1.25 LSB, the integral nonlinearity error is less than ±1.5 LSB, the zero point error is less than ±1 LSB, and the conversion rate is 10 MSPS.
Keywords :
CMOS integrated circuits; analogue-digital conversion; errors; integrated circuit design; integrated circuit measurement; 12 bit; analog-to-digital converter fine bit correction; coarse bit correction; conversion rate; differential nonlinearity error; folding-interpolating two-step conversion ADC; high-speed CMOS A/D converters; integral nonlinearity error; zero point error; Analog-digital conversion; Paper technology; Preamplifiers; Pulse amplifiers; Pulse modulation; Sampling methods; Solid state circuit design; Solid state circuits; Switches; Voltage;
Conference_Titel :
Communications, Circuits and Systems and West Sino Expositions, IEEE 2002 International Conference on
Print_ISBN :
0-7803-7547-5
DOI :
10.1109/ICCCAS.2002.1178940
