DocumentCode :
3168239
Title :
Low-power accumulator (correlator)
Author :
Ercegovac, M.D. ; Lang, T.
Author_Institution :
Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
fYear :
1995
fDate :
9-11 Oct. 1995
Firstpage :
30
Lastpage :
31
Abstract :
As part of our research effort in the development of low-energy numerical computing systems, we have considered the accumulator (correlator) discussed by Chandrakasan and Brodersen (see Proc. IEEE, vol. 83, no. 4, p. 498-523, 1995). The operation to be performed is the accumulation (summation) of 1024 samples which have a range from -7 to +7 and are represented in the two´s complement number system. In this paper we describe an implementation which results in a smaller area and energy than that of the previous implementation. We show expressions for the energy consumption and give an example of the reduction achieved for independent and uniformly distributed sample values and a particular standard cell library.
Keywords :
CMOS digital integrated circuits; correlators; digital arithmetic; digital signal processing chips; correlator; energy consumption reduction; low-energy numerical computing systems; low-power accumulator; standard cell library; two´s complement number system; Clocks; Computer science; Correlators; Counting circuits; Energy consumption; Flip-flops; Libraries;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Low Power Electronics, 1995., IEEE Symposium on
Conference_Location :
San Jose, CA, USA
Print_ISBN :
0-7803-3036-6
Type :
conf
DOI :
10.1109/LPE.1995.482451
Filename :
482451
Link To Document :
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