Title :
A low-voltage 32/spl times/32-bit multiplier in dynamic differential logic
Author :
Matsui, M. ; Burr, J.B.
Author_Institution :
STAR Lab., Stanford Univ., CA, USA
Abstract :
A 32/spl times/32 bit multiplier has been designed using dynamic differential logic improved for low voltage operation. Booth 4 encoding has been used to achieve high speed and small area. Using a 0.35 /spl mu/m CMOS process with Vth=0 V for 0.5 V operation, the estimated delay and power dissipation are 7 ns and 20 mW at 100 MHz. A test chip fabricated in a standard double-metal 0.8 /spl mu/m CMOS process with Vth=0.8 V for 5 V operation achieved 13 ns speed and 1.05 W power dissipation at 75 MHz.
Keywords :
CMOS logic circuits; delays; digital arithmetic; multiplying circuits; 0.35 micron; 0.5 V; 0.8 micron; 1.05 W; 100 MHz; 13 ns; 20 mW; 32 bit; 5 V; 7 ns; 75 MHz; Booth 4 encoding; CMOS IC; LV operation; delay; double-metal CMOS process; dynamic differential logic; high speed operation; low-voltage multiplier; power dissipation; Adders; CMOS logic circuits; CMOS process; Clocks; Encoding; Latches; Logic design; Low voltage; MOSFETs; Threshold voltage;
Conference_Titel :
Low Power Electronics, 1995., IEEE Symposium on
Conference_Location :
San Jose, CA, USA
Print_ISBN :
0-7803-3036-6
DOI :
10.1109/LPE.1995.482453
