Title :
Non-planar device architecture for 15nm node: FinFET or trigate?
Author :
Lin, Chung-Hsun ; Chang, Josephine ; Guillorn, Michael ; Bryant, Andres ; Oldiges, Phil ; Haensch, Wilfried
Author_Institution :
IBM Res. Div., T. J. Watson Res. Center, Yorktown Heights, NY, USA
Abstract :
Multi-gate FETs (MuG-FET) such as FinFETs and Trigate FETs have emerged as the most promising candidates to extend the CMOS scaling beyond sub-22nm node. The multi-gate structure has better short channel behaviors due to enhanced electrostatic control from the multiple gates. However, the superior electrostatic control of the MuG-FET will be offset by the parasitic gate-to-source/drain capacitance (Cgs). Careful device design and optimization of MuG-FET are necessary to achieve an overall performance advantage over conventional planar technology. In this paper, we evaluated the FinFET and Trigate at 15nm node dimension with consideration of electrostatic behavior, parasitic capacitance and resistance using wellcalibrated TCAD simulations.
Keywords :
CMOS integrated circuits; MOSFET; CMOS scaling; FinFET; MuG-FET; device design; enhanced electrostatic control; multigate FET; multigate structure; nonplanar device architecture; optimization; parasitic gate-to-source/drain capacitance; short channel behaviors; trigate FET; Electrostatics; FinFETs; Logic gates; Parasitic capacitance; Performance evaluation; Resistance;
Conference_Titel :
SOI Conference (SOI), 2010 IEEE International
Conference_Location :
San Diego, CA
Print_ISBN :
978-1-4244-9130-8
Electronic_ISBN :
1078-621x
DOI :
10.1109/SOI.2010.5641060